Next-generation gallium nitride (GaN) high electron mobility transistors (HEMTs) require aggressive scaling of device dimensions to reduce device delays, access resistances, and parasitic capacitances for improved high-frequency performance. In particular, ultra-short nanometer-scale gate length and source-drain spacing are required. Also needed is a robust, high throughput, reproducible, and reliable process for such small geometries. Conventionally, high-frequency GaN HEMTs are fabricated using e-beam lithography, metal evaporation and lift-off for T-shaped gate formation. However, using the conventional fabrication processes, the aspect ratio h/Lg defined by the ratio of height (h) 11 of the gate and length 13 of the gate foot (Lg), as shown in height of FIG. 1B, is limited, which decreases the gate head-to-channel distance, giving rise to parasitic capacitances. Furthermore, device uniformity, yield, and minimum gate length relies on alignment accuracy and resolution of e-beam lithography tools, limiting minimum dimensions of scaled devices.
The aspect ratio of conventional T-shaped gates is limited to less than three (3) due to process limitations of the conventional processes.
What is needed is a reliable process for the metallization of high aspect ratio gates in order to increase the performance of field effect transistors and in particular GaN HEMTs. The embodiments of the present disclosure answer these and other needs.